1. Field of the Invention
The present invention relates to a memory system and, more particularly, to a multi-value memory system using a nonvolatile semiconductor memory which is electrically erasable and programmable.
2. Description of the Related Art
In recent years, as a memory system, a semiconductor memory device using a semiconductor memory is popularly used. In the semiconductor memory device, degradation of reliability caused by various influences with a high degree of integration and a high integration density is posed as a problem.
For this reason, an error detection/correction code for performing error detection/correction is often applied to a semiconductor memory device. In practice, this error detection/correction code must satisfy all the following conditions.
(1) An error frequency is lower than a permissible error frequency unique to a semiconductor memory device.
(2) Coding and decoding can be performed at a high speed with a high-speed reading/writing operation.
(3) In code structure, the redundancy of the code is minimum.
For the above practical viewpoints, an SEC-DED code for correcting a 1-bit error and detecting a 2-bit error has been popularly used at present.
In order to obtain higher reliability, a DEC code for correcting a 2-bit error is applied. In particular, a byte error detection/correction code for detecting/correcting errors in units of memory packages or units of multi-bit outputting/storing elements. In order to practically use a device for processing data in units of bytes, an SbEC-DbED code for not only correcting a single-byte error but also having high capability of detecting a 2-byte error is required.
As available means for high integration, a method of multi-value storage has been considered.
In an example of multi-value dynamic semiconductor memory, a memory cell performs a multi-value storage by having three or more dispersed charge distribution stored in the memory cell. In this case, since data stored in one memory cell will be destroyed by one soft error, error correction code (e.g., byte error correction code which treats one cell data as one byte) capable of correcting the above error is required.
On the other hand, in a case of a non-volatile semiconductor multi-value memory device which is electrically erasable and programmable, a memory cell having three or more disperse threshold voltage distribution is used. For example, a multi-value ROM (read only memory) of 3-bit which is constructed by two ternary memory cells is known (Jpn. Pat. Appln KOKOKU Publication No. 5-60199), a multi-value EEPROM can construct the same as the multi-value ROM. For example, 3-bit information can be stored for two memory cells by using eight values from nine values (i.e., 3.times.3=9), as cell group constructed by adjacent memory cells sharing their control gates is a fundamental element. In this case, the multi-value EEPROM differs from the multi-value dynamic semiconductor memory device and has not a problem of soft error. However, charge amount stored in a charge storage layer shifts to a threshold voltage of the memory cell whose charge amount is 0, whereby data error will be raised.
The structure and operation of a ternary NAND EEPROM which can be integrated at a high density will be briefly described below. FIG. 1 is a sectional view showing a NAND cell structure. A NAND cell has a p-type substrate 11, a floating gate 14, a control gate 16, an interlaminar insulating film 17, a bit line 18, and an n-type diffusion layer 19.
A plurality of memory cells are connected in series with each other such that adjacent memory cells commonly use a source and a drain, and the adjacent memory cells are connected to a bit line as one unit, thereby constituting the NAND cell. A memory cell array is integrally formed in a p-type well formed in a p-type substrate or an n-type substrate. The drain side of the NAND cell is connected to bit lines through selection gates, and, similarly, the source and drain sides of the NAND cell are connected to a source line through selection gates. The control gates of the memory cells are continuously arranged in a row direction to constitute word lines.
The operation of the ternary NAND EEPROM is as follows.
A data writing operation is performed from a memory cell located at a position farthest from the bit line. A high voltage Vpp (=about 20 V) is applied to the control gate of a selected memory cell, an intermediate voltage Vm (=about 10 V) is applied to the control gate and selection gate of a memory cell closer to the bit line than the selected memory cell, and a voltage of 0 V, a low voltage Vdd (=about 2 V), or an intermediate voltage is applied to the bit line in accordance with data. When the voltage of 0 V or the low voltage Vdd (=about 2 V) is applied to the bit line, the potential of the bit line is transmitted to the drain of the selected memory cell, and electrons are injected from the drain into the floating gate. In this manner, the threshold voltage of the selected memory cell is positively shifted. However, a shift amount obtained when the low voltage Vdd is applied to the bit line is smaller than a shift amount obtained when the voltage of 0 V is applied to the bit line. When an intermediate voltage is applied to the bit line, no electron injection occurs, and the threshold voltage does not change.
A data erasing operation is simultaneously performed for all the memory cells in the NAND cell. More specifically, all the control gates are set to be 0 V, and the bit and source lines are set in a floating state, thereby applying a high voltage Vpp (=about 20 V) to all the selection gates, a p-type well and an n-type substrate. In this manner, the electrons in the floating gates of all the memory cells are discharged into the p-type well, and the threshold voltage is negatively shifted.
A data reading operation is performed by two cycles. In the first cycle, the control gate of a selected memory cell is set to be 0 V, and the control and selection gates of the remaining memory cells are set to be a power supply voltage Vcc (=about 5 V). In this state, it is checked whether a current flows in the selected memory cell. In the second cycle, the control gate of the selected memory cell is set to be a low voltage Vdd (=about 2 V), and the control and selection gates of the remaining memory cells are set to be the power supply voltage Vcc (=about 5 V). In this state, it is checked whether a current flows in the selected memory cell. In this case, three threshold voltages Vt satisfy Vt&lt;0 V, 0 V=&lt;Vt&lt;Vdd, and Vdd=&lt;Vt&lt;Vcc, respectively.
When i-th data obtained upon arrangement of the magnitudes of physical amounts (e.g., the threshold voltage of a memory cell of EEPROM) for determining multi-values in a descending order is defined as multi-value data "i", a case wherein read-out multi-value data is different from written multi-value data by only one in size is considered. At this time, read-out output data may be different from written input data by 2 or more bits. As a result, at least an SbEC code is required as an error correction/detection code using input/output data as information data. In addition, in order to obtain reliability almost equal to that of an SEC-DED code used in a binary storing element, an SbEC-DbED code is required. However, this SbEC-DbED code requires a complex decoding circuit.
When a burst error such as a column failure of stored data occurs, the net capability of correcting/detecting an error decreases. When such a burst error occurs, and stored data except for the stored data at an address at which the burst error occurs has an error, at least a 2-bit error correction code must be applied to correct these errors.
For example, in a electrically erasable and programmable nonvolatile semiconductor memory (EEPROM), a unique column failure may occur. This column failure occurs when current leaks from a bit line, or data in memory cells in a common column in a block are excessively written or excessively erased. When such a column failure occurs, and a memory cell except for the memory cell at the column address at which the column failure occurs has an error, these errors cannot be corrected by a single b-bit byte error correction code such as an SbEC code. In this case, for example, a double b-bit byte error correction code is required. However, this code requires a complex decoding circuit.
As described above, the conventional memory system has the following problems.
When i-th data obtained upon arrangement of the magnitudes of physical amounts for determining multi-values in a descending order is defined as multi-value data "i", and read-out multi-value data is different from written multi-value data by only one in size, read-out output data may be different from written input data by 2 or more bits. As a result, at least an SbEC code is required as an error correction/detection code using input/output data as information data. In addition, in order to obtain reliability almost equal to that of an SEC-DED code used in a binary storing element, an SbEC-DbED code is required. However, this SbEC-DbED code requires a complex decoding circuit.
In an EEPROM, a unique column failure may occur. When such a column failure occurs, and a memory cell except for the memory cell at the column address at which the column failure occurs has an error, these errors cannot be corrected by a single b-bit byte error correction code such as an SbEC code. In this case, for example, a double b-bit byte error correction code is required. However, this code requires a complex decoding circuit.